Senior Verification Engineer (Remote)

<p>We’re looking for a Senior Verification Engineer to play a key role in verifying complex SoC and subsystem designs. You’ll work hands-on with design and architecture teams to ensure functionality, quality, and coverage goals are met across multiple projects.</p> <p><strong>Responsibilities</strong></p> <ul> <li>Analyze architectural specifications and define verification requirements.</li> <li>Develop and maintain UVM-based verification environments.</li> <li>Create detailed test plans and develop corresponding test cases.</li> <li>Debug functional issues and contribute to root-cause analysis.</li> <li>Collaborate closely with design and architecture teams to align milestones and quality metrics.</li> </ul> <p><strong>Qualifications</strong></p> <ul> <li>Bachelor’s or Master’s degree in EE, CS, or a related field.</li> <li>7–10+ years of experience in verification or similar roles.</li> <li>Strong SystemVerilog and UVM expertise.</li> <li>Familiarity with Linux and standard EDA tools.</li> <li>Thorough understanding of the pre-silicon design and verification flow.</li> <li>Excellent communication, documentation, and teamwork skills.</li> </ul> <p><strong>Preferred / Plus</strong></p> <ul> <li>Proven experience with coverage closure.</li> <li>Background in debugging complex designs.</li> <li>Strong analytical and problem-solving mindset.</li> </ul>